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What is your current simulation/verification tool?
Cadence NC-Sim
Cadence Incisive
Mentor Graphics ModelSim
Mentor Graphics Questa
Synopsys VCS
Aldec Active-HDL
Aldec Riveria
None
Other
Which design language do you use for verification?
SystemVerilog
Verilog
VHDL
SystemC
C/C++
Vera
e
When do you plan to implement the OVM?
Less than 3 months
3 to 6 months
6 to 12 months
More than a year
No plan / Unsure
Comments
Yes, I'd like to receive OVM news and updates
Please have a Cadence Representative Contact Me
Please have a Mentor Graphics Representative Contact Me
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