Components with multiple interfaces

[maxlin]

Hi,

Components sometimes have more than just one interface, e. g. one for data flow and the other one for control information.
I'd like to implement this with several ovm_*_imps which forward to different tasks (say, put() for data flow und control_put() for control information).

Initially, I came up with this "solution":



class control_put_imp #(type T = int, type IMP = int)
extends ovm_blocking_put_imp #(T, IMP);

local IMP m_imp;

function new(string name, IMP imp);
super.new(name, imp);
m_imp = imp;
endfunction : new

task put(input T t);
m_imp.control_put(t);
endtask : put

endclass : control_put_imp
but, unfortunately, this doesn't work:



# ** Error: (vsim-3978) .../ovm/ovm-1.0/src/tlm/ovm_imps.svh(37): Illegal assignment to variable of class xxx_trx from variable of class yyy_trx
The next version does work, but will probably break when OVM internals change:



//
// we can not include src/tlm/tlm_ifs.svh to define `TLM_BLOCKING_PUT_MASK
// because mixing package and include technique will result in type errors
// (ovm_pkg::ovm_... vs. ovm_...)
//

class control_put_imp #(type T = int, type IMP = int)
extends ovm_port_base #(tlm_if_base #(T, T));

local IMP m_imp;

function new(string name, IMP imp);
super.new(name, imp, OVM_IMPLEMENTATION, 1, 1);

m_if = this;
m_imp = imp;
m_if_mask = (1<<0); //`TLM_BLOCKING_PUT_MASK;
m_if_name = "tlm_blocking_put";
assert(this.m_connector.add_if(m_if));
endfunction

task put(input T t);
m_imp.control_put(t);
endtask

endclass
Is there a cleaner way to implement such a functionality?

Thank you!
m.

[tfitz]

Is there a cleaner way to implement such a functionality?


You are right that your second proposal is too dependent on OVM internals to be the right way to go. Instead, we suggest that you wrap the two interfaces in your component, similar to how the ovm_in_order_comparator (src/methodology/ovm_in_order_comparator.sv) handles things.

The key is to have separate data_export and control_export exports. In the ovm_in_order_comparator, these two exports are connected to tlm_analysis_fifos (because these are analysis_exports), and your control and data logic can simply do a get() from the appropriate fifo at the right time. If you want a similar capability using put(), you can instantiate tlm_fifos and pass their put_exports up to the parent.

If you want, you could create your own child ovm_component with the put_export you want. You can pass some other data structure into this child component and implement the child’s put() method to fill this data structure, which can then be used by the appropriate code in the parent. Using tlm_fifos is probably easier.

[maxlin]

I went with the fifo approach abstracting stuff away in a parent class, thus the additionally required amount of scaffolding isn't that bad.

Thank you for your suggestions!

<semi-offtopic>Semi-Off topic:
Is there a discussion to add delegates to SystemVerilog in one of the next versions?
</semi-offtopic>

[dave_59]

<semi-offtopic>Semi-Off topic:
Is there a discussion to add delegates to SystemVerilog in one of the next versions?
</semi-offtopic>

The SV-EC (http://www.eda-stds.org/sv-ec/) is the technical committee where this discussion would take place.

Since the OO model in SystemVerilog was heavily infulenced by Java, I've heard talk about adding Java Interfaces. I don't think I've ever heard talk about C# delegates.

Dave