How to setup / use do_unpack() & do_pack() task?

[JDH]

Hi,
Who knows the usage of do_unpack() & do_pack()?
I need use it for bit-stream convert. I know the Specman language has very good manual to explain them, and implement some communication models. The Specman has MSB or LSB converting directory option in those tasks.
If you have some examples, please give me a favor to post them. Thank you a lot in advance.

Best Regards,
Jeendar

[dave_59]

Jeendar,

SystemVerilog has some new operators and data types that can be used along with traditional Verilog concatenation and bit operations that are very powerful when used together.

You want to look at sections 4.16 Bitstream casting and 8.17 Streaming operators (pack/unpack) of the 1800-2005 LRM.

I typically create bitstream types as

typedef bit bitstream_t[$];
typedef byte bytestream_t[$];

and use whichever type is most applicable to by design. Here's an example


typedef byte bytestream_t[$];// [DR] generic stream of bytes type

class Packet;

rand bit [31:0] header;
rand bit [31:0] stuff; // bit part of pack/unpack
rand bit [7:0] length;
rand bit [7:0] payload[];
constraint G { length inside {[1:9]}; payload.size == length ; }
constraint even_parity { ^header == 0;}

virtual function bytestream_t pack();
pack= {<< byte {header,length,payload}}; // packs in reverse byte order
endfunction : pack

virtual function void unpack( bytestream_t pack);
{ << byte {header, length, payload}} = pack; // unpacks in reverse byte order
endfunction : unpack
virtual function void print();
$display("%p", this);
endfunction

endclass : Packet

class Packet_crc extends Packet;
int crc;
function void post_randomize; crc = payload.sum; endfunction

// one way to extend a method
virtual function bytestream_t pack();
bytestream_t tmp = {<< byte {crc}};
pack= '{tmp, super.pack}; // packs in reverse byte order
endfunction : pack

// another way to extend a method - re-write it
virtual function void unpack( bytestream_t pack);
{ << byte {header, length, payload , crc}} = pack; // unpacks in reverse byte order
endfunction : unpack
endclass : Packet_crc


module pup();


Packet P1, P2;
Packet_crc P3, P4;

initial
begin
P1 = new();
assert(P1.randomize());
P1.print;
P2 = new();
P2.unpack(P1.pack()); //Pack UnPack
P2.print;
P3 = new();
P1 = P3;
assert(P1.randomize());
P1.print;
P4 = new();
P4.unpack(P1.pack()); //Pack UnPack
P4.print;
end

endmoduleDave

[JDH]

Dave,
Very thank your response.
I known the ">>" or "<<" commands for pack/unpack in SystemVerilog. But the OVM has do_pack() and do_unpack() function call in ovm_object class. I guess it has more power function than SystemVerilog pack/unpack commands. So, I hope more information or examples to understand them.
BTW, I very thank your time to response this example.
Jeendar

[devangamoneesh]

Hi Dave,

I have coded accordingly in my protocol, In this example they used bytestream fifo for using pack function, but the error its showing is
1: Here bytestream used as
typedef byte bytestream_t [$] ; ----- and error is
" Using queues, associative arrays, dynamic arrays and strings with the stated construct has not yet been implemented "
2:and pack declared as
pack= {<< byte {header,length,payload}}; ---- and error is
" illegal expression primary "

Now what i have to do ?


Thanks in advance
Regards,
Moneesh

[dave_59]

Hi Moneesh,

I find it hard to believe that a simulator that supports SystemVerilog wouldn't support queues. Try using a different simulator. :)

There must be something else going on interfering with that statement. Try using just a bit or bit [7:0].

The streaming operator can be replaced with complex series of nested for loops that do the transfer one bit at a time. An exercise left for the reader!

Dave

[lalkumar_b]

Hi Dave,
I need examples using pack and unpack ovm_object. what is the meaning of ovm_filed property called PHYSICAL? does it similar to specman(e) physical fields? if that is the case why doesn't work pack and unpack methods on physical fields? Is it intension of physical fields.

regards
Lal