Assertions in classes

[kunal1514]

Hi All,

Can we define assertions in classes

[gordon]

No, unfortunately not. See this post on SVUG (http://www.svug.org/Forum/tabid/57/forumid/26/postid/56/view/topic/Default.aspx) for explanation and discussion.

Cheers,

[tfitz]

You can, however, have concurrent assertions in modules or interfaces and connect those through TLM to the rest of your class-based verification environment. See Chapter 9 of The Verification Cookbook for a discussion of this topic. I'm sure there are other resources out there that also discuss how to do this, but the Cookbook is my personal favorite. ;)

[kunal1514]

Hi All,

It's confusing one is saying "No" to define assetions in Classes

other one is saying "Yes" to define assertions in Classes.

Who is correct i don't know.

Regards

[kurts]

There really is not a conflict in those answers.

You cannot declare assertions in classes. Assertions are always "on" and watching the activity in your design, and classes are dynamic things - they come and go during runtime.

What Tom said is that you *can* put assertions in modules and interfaces. Those things are not dynamic. They are not classes. They exist from the start of simulation through to the end, so they are allowed to have assertions in them.

Tom also said that even though you can't declare assertions in classes, you can make use of assertions indirectly from within classes. For example, you can trigger an event when a sequence is recognized that wakes up some code which calls class-based tasks and functions. As Tom said, there are examples of how to do things like this in the AVM cookbook.

I hope this clears things up a little,
-Kurt