Mixed language support

[gaurav.gajjar@einfochips.com]

Hi,

I want to know about the mixed language support with OVM. I just want to know that when this feature will be supported by OVM? I will appreciate your reply or any kind of update regarding this.

Thanks & Regards,
Gaurav Gajjar

-------------------------------------------------------
Hi ,

I mean to say mixed language support i.e. e , SV etc... .
So I want to convert e code to be OVM complient.
Is there any update for converting the e code to OVM or when it will be available ?

Thanks & Regards;
Gaurav Gajjar

[ajeetha]

Gaurav,
Not sure what you are asking for is valid in the context of SystemVerilog on its own - SV as a language does not allow E-code comptability (or VHDL). However you are correct about a methodology should alllow this. For instance URM allows such a mix - infact some of the lower layers can be in E while top layer can be in SV. Hence OVM also should allow that in principle (though I have not used it). However that's a tool/implementation specific extension I would say. IUS allows it, infact recently IUS allows e-to-SV interoperability by which one can extend an e-struct inside SV env! Look for it in recent IUS documentation for more.

Also note that SV-SystemC interaction is allowed by all major tools. With OVM this could mean that the producer of a tlm_fifo can be SV and the consumer is SystemC.

When it comes to VHDL, there is no standard for mixed language, but tools have been supporting it for many years and Questa allows nice mix of them.

HTH
Ajeetha, CVC
www.noveldv.com

[gaurav.gajjar@einfochips.com]

Hi Ajeetha,

Yes URM allows that but I am asking about the OVM methodology , in OVM methodology what will be the steps to use my eRM compliant component in the OVM environment.

They explained in OVM webcast that eRM compliant component can be a part of whole verification testbanch.

Thanks & Regards:
Gaurav Gajjar

[stuart]

The OVM is based on the AVM and the URM and both have established mechanisms to facilitate interoperability between languages such as SystemVerilog, SystemC, 'e' and VHDL. Since OVM builds on both of them, it has the inherent architecture to support multiple languages, but we chose not to include the implementations in OVM 1.0 to meet the January release.

So, for now, you'll need to contact your EDA vendor to understand what multi-language interoperability capabilities are available to use with the OVM. As we have mentioned, we are planning an update to the OVM and multi-language support is one item being considered.

-Stuart

[gaurav.gajjar@einfochips.com]

Hi Stuart,

Thanks for the information.
I will contact my EDA vendor .

Thanks & Regards;
Gaurav Gajjar

[signalscan4ever]

The OVM is based on the AVM and the URM and both have established mechanisms to facilitate interoperability between languages such as SystemVerilog, SystemC, 'e' and VHDL. Since OVM builds on both of them, it has the inherent architecture to support multiple languages, but we chose not to include the implementations in OVM 1.0 to meet the January release.
-Stuart

If I may pose a slighty off-topic question -- can a (non-OVM) Systemverilog-model be used in an eRM environment? I.e., in Incisive Enterprise Simulator 6.2 (irun), can an eRM-testbench include Systemverilog-RTL files (which use SVA, covergroups, and some other Systemverilog testbench langauge features)?

I would love to give OVM a trial, but our current partner is heavily invested in eRM!

[zeevk]

If I may pose a slighty off-topic question -- can a (non-OVM) Systemverilog-model be used in an eRM environment? I.e., in Incisive Enterprise Simulator 6.2 (irun), can an eRM-testbench include Systemverilog-RTL files (which use SVA, covergroups, and some other Systemverilog testbench langauge features)?

I would love to give OVM a trial, but our current partner is heavily invested in eRM!

Heavy investments in eRM are not a bad thing... :)
Seriously, the URM methodology was used to show such reuse (SystemVerilog components inside a larger eRM environment) for quite a while now. Assuming you have IPCM installed, take a look at the examples located under $IPCM_HOME/urm_lib/mixed_ex_lib.
The next release of IPCM will show even more such mixed e/SV examples, based on OVM.

Regards,

Zeev.

[gaurav.gajjar@einfochips.com]

Hi ..

It's really true .... "Heavy investments in eRM are not a bad thing" ...

Because we have a sollution for reuse that investment using uvc developed by systemverilog API's.
uVC provides the interface bet'ween specman and the systemverilog.
If some one is not knowing the "e" and also dont want to learn "e" or they have verification testbench in SV and they want to use eVC in it so they can develop the wrapper which will allow the user to write test cases in SV and it will run in eVC component.

You can monitor the data also from the eVC to SV environment, and ultimetly you can write the coverage also.

Also see example which Zeev told.
It will help you....Best Luck:)

Best Regards;
Gaurav Gajjar (eInfochips)