gFaurie
01-28-2008, 08:49 AM
Hy,
I am working on an IUS based SystemVerilog OVM verification environment. This environment is completely working with IUS using the OVM 1.0 libraries and I am currently trying to run the same environment using Questa 6.3d.
After some "little" adaptations, the compilation is now running well and I am facing an error when launching simulation:
# ** Error: (vsim-3978) /home/faurie/Methodology/ovm-1.0/src/base/ovm_registry.svh(29): Illegal assignment to String from class
This file is part of OVM package so I don't want to modify it, can you help me understand the error origin?
Regards,
Geoffrey
I am working on an IUS based SystemVerilog OVM verification environment. This environment is completely working with IUS using the OVM 1.0 libraries and I am currently trying to run the same environment using Questa 6.3d.
After some "little" adaptations, the compilation is now running well and I am facing an error when launching simulation:
# ** Error: (vsim-3978) /home/faurie/Methodology/ovm-1.0/src/base/ovm_registry.svh(29): Illegal assignment to String from class
This file is part of OVM package so I don't want to modify it, can you help me understand the error origin?
Regards,
Geoffrey