Using OVM and 'e' in same testbench?

[signalscan4ever]

I'm new to Systemverilog verification (and OVM, in particular.) I'm also new to the 'e' Verification language.

My company uses Incisive 6.2 -- I realize that it's best to stick with ONE TLM-modeling system (OVM, uRM, or eRM), but can 'e' be used with a simulation-environment containing Systemverilog? Or are the two mutually exclusive?

[stuart]

There was already some discussion about multi-language capabilities of OVM in the following thread:

http://www.ovmworld.org/forums/showthread.php?t=16

In a nutshell, interoperability between 'e' and OVM SV models is possible today, but for now you'll need to contact your EDA vendor to understand what is currently available.

-Stuart